Semiconductor hall sensor

ABSTRACT

A semiconductor Hall sensor can reduce measuring error due to an unbalanced voltage by decreasing the unbalanced voltage, and improve resistance to electrostatic by suppressing maximum electric field in the sensor. A cross-shaped pattern of the semiconductor Hall sensor includes cutouts at its concave corners. Among the four concave corners of the cross-shaped pattern, consecutive two or four concave corners are provided with the cutouts. Besides, among the four concave corners of the cross-shaped patterns, the consecutive two or four concave corners have an acute angle at the intersection of the input terminal side pattern and output terminal side pattern. The semiconductor Hall sensor becomes insensitive to defects or unbalance of its pattern, thereby being able to reduce the unbalanced voltage as compared with a conventional cross-shaped pattern of the semiconductor Hall sensor.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor Hall sensor, andmore particularly to pattern geometry of a semiconductor Hall sensor.

BACKGROUND ART

[0002] Conventionally, semiconductor Hall sensors are widely used asrotating position detecting sensors of drive motors for VTRs, floppies(registered trademark) and CD-ROMs, or as potentiometers and gearsensors. As their magneto-sensitive films, are used InSb (indiumantimonide) with high mobility and sensitivity, and GaAs (galliumarsenide) with large energy bandgap width and good temperaturecharacteristic.

[0003] The semiconductor Hall sensor is one of the magnetic sensors,which has a characteristic of producing a Hall output voltageproportional to magnetic flux density in the direction perpendicular toa magneto-sensitive plane. Accordingly, the Hall output voltage shouldbe zero when no magnetic field is present. However, in actuality thesemiconductor Hall sensor can sometimes generate the Hall output voltagewhen applied with an input voltage even without the magnetic field. Thevoltage is called an unbalanced voltage (Vu).

[0004] The unbalanced voltage, which constitutes DC noise superimposedon the Hall output voltage, causes measuring error of the semiconductorHall sensor. In addition, there are some cases where Si integratedcircuit must be used to correct the unbalanced voltage in order to zerothe Hall output voltage when no magnetic field is present, whichpresents a problem of cost and size.

[0005]FIG. 11 is a cross-sectional view showing a structure of aconventional semiconductor Hall sensor using a semi-insulating GaAssubstrate. On the top surface of a semi-insulating GaAs substrate 11,selective ion implantation of Si or the like is carried out, or amagneto-sensitive film 12 composed of InSb, InAs (indium arsenide) orGaAs is formed by MBE (molecular beam epitaxy) or MOVPE (metal organicvapor phase epitaxy). Then, it is processed to a desired pattern byphotolithography. Subsequently, an inorganic protective film 14 composedof SiO₂ or SiN and internal electrodes 13 for passing a current areformed on the magneto-sensitive film 12, followed by dicing and diebonding. Then, wires 17 are connected to the electrodes 13, followed bymolding with a resin 16. In FIG. 11, the reference numeral 15 designatesa lead frame.

[0006] As described above, the magneto-sensitive pattern of thesemiconductor Hall sensor is formed by patterning the magneto-sensitivefilm by the photolithography, followed by etching. The unbalancedvoltage usually occurs because of geometric unbalance of a devicegeometry, which is produced during the patterning of the semiconductorHall sensor. A leading cause thereof is that the pattern of thesemiconductor Hall sensor drawn on the mask pattern is not in perfectagreement with the pattern of the actually fabricated semiconductor Hallsensor because of etching accuracy and the like.

[0007] To solve the problem, Japanese Patent Application Laid-open No.1-298354, for example, discloses a method of chamfering four concavecorners of a cross-shaped Hall device pattern (see, FIG. 8).

[0008]FIG. 2 is a diagram showing a pattern of a conventionalsemiconductor Hall sensor. At concave corners of a cross-shaped pattern21, an input terminal side pattern forms a right angle of 90 degreeswith an output terminal side pattern. The pattern of the semiconductorHall sensor uses vertical electrodes as input side terminals, andhorizontal electrodes as output side terminals.

[0009] Here, the length and width of the input terminal side pattern aredenoted by L1 and W1, and the length and width of the output terminalside pattern are denoted by L2 and W2. More strictly, L1 and L2 arepattern distances of the semiconductor Hall sensor pattern across theelectrodes, and W1 and W2 are defined as a greater one of the patternwidth of the semiconductor Hall sensor and the pattern width of portionsof the semiconductor Hall sensor contacting the electrodes.

[0010] Besides the chamfering, a method is known of reducing theunbalanced voltage by varying the ratio L/W of the length L and width Wof the cross-shaped semiconductor Hall sensor pattern (in this example,it has a symmetric input/output pattern. Namely, L1=L2=L, W1=W2=W).

[0011] Generally, the unbalanced voltage generally reduces with anincrease in L/W. However, an increasing L/W causes a new problem ofincreasing the size of the semiconductor Hall sensor. In addition, anincrease in the L/W reduces the sensitivity (the output voltage under aspecified magnetic flux density) of the semiconductor Hall sensor, whichalso presents a problem. In this method, since the rate of reduction ofthe unbalanced voltage is greater than that of the sensitivity, thesignal-to-noise ratio is on the decrease, which means that the method isnot suitable for a high accuracy measurement. Consequently, it is not adecisive method of reducing the unbalanced voltage.

[0012] Furthermore, the GaAs semiconductor Hall sensor or the like has aproblem of a poor resistance to electrostatic as compared with theSi-composed integrated circuit (IC). The electric field takes a maximumvalue at concave corners of the pattern of the cross-shapedsemiconductor Hall sensor. Thus, it is thought that the currentconcentrates to the concave corners, thereby causing a problem ofdestroying the device.

[0013] The foregoing method disclosed in Japanese Patent ApplicationLaid-open No. 1-298354 is effective for rather inaccurate etching likewet etching that is isotropic. However, dry etching with high anisotropyhas been developed recently which utilizes ion milling or ECR (electroncyclotron resonance), thereby improving the etching accuracy. As aresult, nearly ideal etching becomes possible, and hence the device withan almost identical geometry to the mask pattern can be formed.Therefore it is necessary to consider the pattern of the semiconductorHall sensor capable of reducing the unbalanced voltage not empiricallybut theoretically.

[0014] The present invention is implemented in view of the foregoingproblems. Therefore an object of the present invention is to provide asemiconductor Hall sensor capable of reducing the unbalanced voltage,and the measuring error resulting from the unbalanced voltage, and toimprove the resistance to electrostatic.

DISCLOSURE OF THE INVENTION

[0015] The inventor of the present invention studied a pattern of thesemiconductor Hall sensor that can reduce the unbalanced voltage througha simulation analysis and semiconductor Hall sensor prototypes. As aresult of the simulation analysis, it was found theoretically that whenthe pattern of the semiconductor Hall sensor had defects or unbalance,the pattern of the semiconductor Hall sensor described in the foregoingJapanese Patent Application Laid-open No. 1-298354 with the chamfersincreased the unbalanced voltage as compared with an ordinarycross-shaped Hall sensor pattern. The results will be described later ina comparative example 1.

[0016] Furthermore, the inventor of the present invention found patternsof the semiconductor Hall sensor, which were able to reduce theunbalanced voltage as compared with the conventional cross-shapedpattern or the pattern with the chamfers. In addition, inventor foundsthat the patterns of the semiconductor Hall sensor improved theresistance to electrostatic as well, thereby accomplishing the presentinvention.

[0017] To accomplish the objects of the present invention, according toa first aspect of the present invention, there is provided asemiconductor Hall sensor having a cross-shaped pattern that includes aninput side pattern with a length and width of L1 and W1, and an outputside pattern with a length and width of L2 and W2, the semiconductorHall sensor being characterized in that: a film thickness, impurityconcentration, the length L1 and width W1 of the input side pattern andthe length L2 and width W2 of the output side pattern are maintained;and at least one of a resistance across input side terminals and aresistance across output side terminals is made 1.25 to 2.75 times aresistance of a cross-shaped pattern consisting of a rectangle with thelength L1 and width W1 serving as the input side pattern, and arectangle with the length L2 and width W2 serving as the output sidepattern.

[0018] Thus placing the resistances of the input side pattern and outputside pattern within the foregoing range can improve its characteristicby a few tens of percent as compared with the cross-shaped patternwithout cutouts, when evaluated in terms of S/N, one of the mostimportant characteristics of the Hall device.

[0019] In a range less than 1.25 times, the reduction effect of theunbalanced voltage is insufficient. In addition, when it is greater than2.75 times, although the reduction in the unbalanced voltage is large,the S/N is deteriorated because of the reduction in signal component. Asa result, the resistance is preferably in the range of 1.25 to 2.75times.

[0020] According to a second aspect of the present invention, there isprovided a semiconductor Hall sensor having a cross-shaped pattern thatincludes an input side pattern with a length and width of L1 and W1, andan output side pattern with a length and width of L2 and W2, thesemiconductor Hall sensor comprising: at least one type of cutouts atconsecutive two or four concave corners among four concave corners of across-shaped semiconductor Hall sensor, the cutouts having a geometry ofone of a square, polygon, circle, ellipse and a combination of theseforms, wherein the semiconductor Hall sensor is characterized in that: afilm thickness, impurity concentration, the length L1 and width W1 ofthe input side pattern and the length L2 and width W2 of the output sidepattern are maintained; and at least one of a resistance across inputside terminals and a resistance across output side terminals is 1.25 to2.75times a resistance of a cross-shaped pattern consisting of arectangle with the length L1 and width W1 serving as the input sidepattern, and a rectangle with the length L2 and width W2 serving as theoutput side pattern.

[0021] More preferably, both the resistance across the input sideterminals and the resistance across the output side terminals may be 1.5to 2.5 times the resistance of the cross-shaped pattern consisting ofthe rectangle with the length L1 and width W1 serving as the input sidepattern, and the rectangle with the length L2 and width W2 serving asthe output side pattern.

[0022] The foregoing range can improve the S/N of the Hall sensor by 30%or more. This makes it possible to suppress the characteristicvariations to the same level achieved when a canceling circuit forsuppressing the characteristic variations of the Hall IC is used,without using the canceling circuit of the unbalanced voltage. Inaddition, the resistance to electrostatic is improved markedly.

[0023] More preferably, the consecutive two or four concave corners ofthe four concave corners of the cross-shaped pattern may have an acuteangle at an intersection of the input terminal side pattern and theoutput terminal side pattern of the cross-shaped pattern.

[0024] As a method of calculating the resistance of pattern geometry, anelectrostatic field analysis using a finite-element method is effective.The resistance can be calculated by modeling the device geometry,analyzing the state that passes the constant current across the input oroutput terminals, calculating the voltage drop occurring at the time,and dividing the voltage drop by the amount of the current (Ohm's law).

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a diagram showing an equivalent bridge circuit of asemiconductor Hall sensor in accordance with the present invention;

[0026]FIG. 2 is a diagram showing a pattern of a conventionalcross-shaped semiconductor Hall sensor;

[0027]FIG. 3 is a diagram showing a pattern of a semiconductor Hallsensor in accordance with the present invention;

[0028]FIG. 4 is a diagram showing another pattern of the semiconductorHall sensor in accordance with the present invention;

[0029]FIG. 5 is a diagram showing still another pattern of thesemiconductor Hall sensor in accordance with the present invention;

[0030]FIG. 6 is a diagram showing another pattern of the semiconductorHall sensor in accordance with the present invention;

[0031]FIG. 7 is a diagram showing another pattern of the semiconductorHall sensor in accordance with the present invention;

[0032]FIG. 8 is a diagram showing another pattern of the conventionalcross-shaped semiconductor Hall sensor;

[0033]FIG. 9 is a diagram showing another pattern of the semiconductorHall sensor in accordance with the present invention;

[0034]FIG. 10 is a diagram showing another pattern of the semiconductorHall sensor in accordance with the present invention;

[0035]FIG. 11 is a cross-sectional view showing a structure of aconventional semiconductor Hall sensor;

[0036]FIG. 12 is a graph illustrating the dependence of the rate ofchange of the standard deviation of the unbalanced voltage on the rateof change of the device resistance of the semiconductor Hall sensor inaccordance with the present invention;

[0037]FIG. 13 is a graph illustrating the dependence of the rate ofchange of the Hall output voltage on the rate of change of the deviceresistance of the semiconductor Hall sensor in accordance with thepresent invention; and

[0038]FIG. 14 is a graph illustrating the dependence of the S/N on therate of change of the device resistance of the semiconductor Hall sensorin accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0039] The embodiments in accordance with the invention will now bedescribed with reference to the accompanying drawings.

[0040]FIG. 1 is a diagram showing an equivalent circuit of asemiconductor Hall sensor. The equivalent circuit can be represented bya bridge circuit using four resistors R1, R2, R3 and R4. In FIG. 1, whena voltage of one volt is applied across input terminals Vi(+) and Vi(−),the outputs at output side terminals Vo(+) and Vo(−) are given by thefollowing expressions (1) and (2).

Vo(+)=R4/(R1+R4)   (1)

Vo(−)=R3/(R2+R3)   (2)

[0041] Since the Hall output voltage is expressed by the differencebetween expressions (1) and (2), the generated unbalanced voltage Vu isgiven by the following expression (3).

Vu=(R2·R4−R1·R3)/(R1+R4)·(R2+R3)   (3)

[0042] To reduce the unbalanced voltage, the value of expression (3)must be reduced. Ideally, if the four resistors R1, R2, R3 and R4 havethe same value, then the unbalanced voltage Vu becomes zero. However,during the etching to form the pattern, a small number of defects andunbalance are produced in the pattern of the semiconductor Hall sensor,which results in a nonzero unbalanced voltage because the resistancesbecome unequal. The variations in the resistors due to the unbalanceremain within a certain limit because of the etching accuracy of formingthe magneto-sensitive portion. Accordingly, to reduce the Vu, it is achoice to reduce the rate of change of each resistor for the samedefects and unbalance.

[0043] To achieve this, the semiconductor Hall sensor in accordance withthe present invention provides cutouts to two or four consecutiveconcave corners of the pattern in such a manner that the cutouts areplaced inside the right angle positions of the concave corners of thecross-shaped pattern as described above. The cutouts can relief theconcentration of the current to the concave corners, thereby reducingthe electric field in the concave corners. Accordingly, even if somegeometric unbalance is present in the pattern of the semiconductor Hallsensor, it can prevent the variations in the electric field, therebyreducing the unbalanced voltage of the semiconductor Hall sensor. Inother words, the cutouts formed at the concave corners, which reduce theelectric field in the concave corners,can make the semiconductor Hallsensor insensitive to the geometric unbalance, and hence reduce theunbalanced voltage. In addition, the reduction in the electric fieldimproves the resistance to electrostatic of the semiconductor Hallsensor.

[0044] The fabrication process of the semiconductor Hall sensor inaccordance with the present invention is the same as the conventionalmethod except for the pattern geometry of the magneto-sensitive portionof the Hall sensor. FIG. 11 shows one of such a semiconductor Hallsensor. Specifically, on the top surface of a semi-insulating GaAssubstrate 11, selective ion implantation of Si or the like is carriedout, or a magneto-sensitive film 12 composed of InSb, InAs (indiumarsenide) or GaAs is formed by MBE or MOVPE. Then, it is processed to adesired pattern by photolithography. Subsequently, an inorganicprotective film 14 composed of SiO₂ or SiN and internal electrodes 13for passing a current are formed on the magneto-sensitive film 12,followed by dicing and die bonding. Then, wires 17 are connected to theelectrodes 13, followed by molding with a resin 16.

EXAMPLE 1

[0045]FIG. 3 is a diagram showing an example of the pattern of thesemiconductor Hall sensor in accordance with the present invention.Since the pattern 1 of the semiconductor Hall sensor has a shape of across, it has four concave corners 2 a. However, in contrast to theconventional pattern of the semiconductor Hall sensor as shown in FIG.2, it has cutouts (removed portions) instead of the right angle concavecorners. With the concave corners without the right angle, the patternof the semiconductor Hall sensor in accordance with the presentinvention can reduce the electric field in the concave corners.

[0046] The cutouts are formed by cutting squares out of the concavecorners. The squares each have a side of 70 μm for the cross-shapedpattern with the length L of 140 μm and a width W of 70 μm. The geometryof the cutouts is not limited to a square: It can take any form as longas it can be shaped by cutting such as a polygon other than a square,circle and ellipse. Unless the cutouts with the same geometry are formedin line symmetry with respect to either the input side pattern or outputside pattern of the cross-shaped pattern, the unbalanced voltage cangenerate contrary to expectations.

[0047] FIGS. 4-7 are diagrams each showing an example of the geometry ofthe cutouts 2 b, 2 c, 2 d and 2 e.

[0048] The maximum electric field in the concave corners when idealetching was performed and when the input voltage of one volt is appliedare as follows. As for the conventional cross-shaped pattern of thesemiconductor Hall sensor, it was 2.338×10⁴ V/m. As for the pattern ofthe semiconductor Hall sensor with the square cutouts, it was 1.644×10⁴V/m, about a 30% reduction in the maximum electric field. In addition,it was confirmed that the pattern was effective to improve theresistance to electrostatic. As for the circular cutouts with a radiusof 35 μm instead of the squares (FIG. 4), the maximum electric field was1.216×10⁴ V/m under the same conditions, which is about 48% reductionfrom that of the conventional cross-shaped pattern.

[0049] In summary, the foregoing results are shown in Table 1 along withthe simulation results of FIGS. 5-7. Focusing attention on theimprovement of the resistance to electrostatic, the geometry of thecircular cutouts was best in the study performed this time. TABLE 1maximum electric field (V/m) 2.338 × 10⁴ 1.644 × 10⁴ 1.216 × 10⁴ 2.221 ×10⁴ 1.683 × 10⁴ 1.396 × 10⁴

[0050] As for the dimensions of the cutouts, any dimensions areconsidered to be effective. In the simulation at this time, the ratiosof the dimensions to (L-W) were set at 0.1-75%, and they were alleffective to improve the resistance to electrostatic. Above all, theratios of 25-75% were particularly effective. In terms of the variationsin the input/output resistance, the effect was remarkable when thevariations were 1.25-2.75 times. Although the simulation at this timeemployed the pattern of the Hall sensor that L/W was two, advantagessimilar to the foregoing results can be surely obtained for the ratiosother than two.

[0051] However, the range of the dimensions of the cutouts for achievingthe improvement of the resistance to electrostatic will vary a littlewith the variation in the value L/W. The foregoing simulation analysiswas performed using an electric resistivity corresponding to InSb(indium antimonide) as a characteristic of the semiconductor Hallsensor. The similar effects were confirmed using the electricresistivity corresponding to InAs (indium arsenide) and GaAs (galliumarsenide).

EXAMPLE 2

[0052]FIGS. 9 and 10 are diagrams showing another example of the patternof the semiconductor Hall sensor in accordance with the presentinvention. As another pattern of the semiconductor Hall sensor forreducing the unbalanced voltage and improving the resistance toelectrostatic other that the foregoing example 1, the example as shownin FIG. 9 or 10 is possible. It includes cutouts 4 a or 5 a in theconcave corners of the cross-shaped pattern, the concave corners havingan acute angle or rounded shape at intersection of the input/outputpattern 41 or 51. The cutouts can offer similar advantages by formingthem in the similar geometry and dimensions to those of the foregoingexample 1.

EXAMPLE 3

[0053] A semiconductor Hall sensor was actually prototyped whichincluded cutouts in the concave corners of a magneto-sensitive portion.The L and W of the pattern of the semiconductor Hall sensor were 140 μmand 70 μm, respectively. The geometry of the cutouts was four types ofFIGS. 3, 5, 6 and 7. The dimensions of the cutouts are 5 μm-35 μm. Inaddition, the method of varying the ratio L/W as a conventional meansfor reducing the unbalanced voltage was carried out as a comparison. Inthis case, the semiconductor Hall sensor patterns were prototyped withthe fixed width W of 70 μm, and with varying the length L in a range of132-280 μm.

[0054] The results are as follows, in which the rate of change of theresistances, the rate of change of the standard deviation of theunbalanced voltage and the rate of change of the output voltage werecomputed with reference to those of the semiconductor Hall sensorpattern with L and W of 140 μm and 70 μm, and without the cutouts. Asexpected, the average of the unbalanced voltage was about zero millivoltfor all the prototype patterns this time. Thus evaluation of thereduction in the unbalanced voltage was made in terms of the standarddeviation of the unbalanced voltage.

[0055]FIG. 12 is a graph whose vertical axis represents the rate ofchange of the standard deviation of the unbalanced voltage, and whosehorizontal axis represents the rate of change of the resistance of thedevice. The rate of change of the standard deviation has littledependence on the geometry of the cutouts. However, it is clear that therate of reduction in the standard deviation of the unbalanced voltage ofeach prototype is greater than that of the conventional method ofvarying L/W, for the same rate of change of the resistance.

[0056]FIG. 13 is a graph whose vertical axis represents the rate ofchange of the Hall output voltage under a particular magnetic fluxdensity, and whose horizontal axis represents the rate of change of theresistance of the device. Although these results have little dependenceon the geometry of the cutouts in this case as well, it is seen that therates of reduction in the output voltages are smaller than in theconventional method of varying the ratio L/W.

[0057]FIG. 14 is a graph whose vertical axis represents the quotientobtained by dividing the rate of change of the output voltage by therate of change of the standard deviation of the unbalanced voltage (rateof change of S/N) under a particular magnetic flux density, and whosehorizontal axis represents the rate of change of the resistance of thedevice. Although these results have little dependence on the geometry ofthe cutouts in this case as well, it is seen that the examples with therate of change of the device resistance of 1.25-2.75 can improve S/N bymore than 20%, and of 1.5-2.5 have more conspicuous effect.

[0058] It is clear from the foregoing results that the semiconductorHall sensors with the cutouts can improve the S/N ratio and enable thehigh accuracy measurement as compared with the conventional method ofvarying the ratio L/W. In addition, the present scheme offers anadvantage of being able to improve the performance without increasingthe size of the semiconductor Hall sensor.

[0059] When the pattern of the semiconductor Hall sensor geometry isgiven, the resistance can be calculated by using a finite-elementanalysis. The resistances of the prototypes of FIG. 3 and FIGS. 5-7 wereobtained using the finite-element analysis. The ratios to the resistanceof the reference pattern with L=140 μm and W=70 μm are shown in Table 2.The calculated results are found to be in good agreement with theexperimental values. TABLE 2 Ration to reference resistances Ration toreference (experimental resistances values) (calculated values) 2.0382.017 1.525 1.513 1.803 1.789 1.840 1.825

COMPARATIVE EXAMPLE

[0060] A study was also made of the unbalanced voltage generated by theconventional pattern of the semiconductor Hall sensor with the chamfers(FIG. 8) disclosed in the foregoing Japanese patent applicationlaid-open No. 1-298354. A simulation analysis was carried out based onthe cross-shaped pattern of the semiconductor Hall sensor as shown inFIG. 2. Specifically, the cross-shaped pattern with the length L of 140μm and width W of 70 μm was used. The pattern had chamfers with theshape of an isosceles right triangle with two sides of 5.0 μm on thefour concave corners of the cross-shaped pattern of the semiconductorHall sensor. Consider cases where the two patterns each have a patterndefect with a shape of an isosceles right triangle with the two sides of5.6 μm at a location 10 μm apart from the upper right concave cornertoward the output terminal side. This assumes that parts of the patternsof the semiconductor Hall sensors are removed because of over etching orthe defect of the resist. The unbalances of the chamfered patternsbrought about the unbalanced voltage of 3.25 mV for the input voltage ofone volt.

[0061] Since the unbalanced voltage of the conventional cross-shapedpattern of the semiconductor Hall sensor was 2.75 mV under the samecondition, the unbalanced voltage increased by about 18%. The simulationanalysis was conducted by using the electric resistivity correspondingto InSb (indium antimonide) as the characteristic of the semiconductorHall sensor. Incidentally, using the electric resistivity correspondingto InAs (indium arsenide) and GaAs (gallium arsenide) brought aboutsimilar results.

INDUSTRIAL APPLICABILITY

[0062] As described above, according to the present invention, theconsecutive two or four concave corners of the cross-shaped pattern havethe cutouts, which make the semiconductor Hall sensor more insensitiveto the defects or unbalance of its pattern. Thus, it can reduce theunbalanced voltage as compared with the conventional cross-shapedpattern of the semiconductor Hall sensor. In addition, it can reduce themaximum value of the electric field of the device in the concave cornersof the pattern of the semiconductor Hall sensor. As a result, it canrelief the current concentration, and hence can improve the resistanceto electrostatic.

[0063] Furthermore, compared with the conventional method of reducingthe unbalanced voltage, which varies the ratio L/W of the semiconductorHall sensor pattern, the present method enables the semiconductor Hallsensor to shrink its size and to improve its S/N ratio. Therefore it canbe safely said that a semiconductor Hall sensor suitable for highaccuracy measurement.

What is claimed is:
 1. A semiconductor Hall sensor having a cross-shapedpattern that includes an input side pattern with a length and width ofL1 and W1, and an output side pattern with a length and width of L2 andW2, said semiconductor Hall sensor being characterized in that: a filmthickness, impurity concentration, the length L1 and width W1 of theinput side pattern and the length L2 and width W2 of the output sidepattern are maintained; and at least one of a resistance across inputside terminals and a resistance across output side terminals is made1.25 to 2.75 times a resistance of a cross-shaped pattern consisting ofa rectangle with the length L1 and width W1 serving as the input sidepattern, and a rectangle with the length L2 and width W2 serving as theoutput side pattern.
 2. A semiconductor Hall sensor having across-shaped pattern that includes an input side pattern with a lengthand width of L1 and W1, and an output side pattern with a length andwidth of L2 and W2, said semiconductor Hall sensor comprising: at leastone type of cutouts at consecutive two or four concave corners amongfour concave corners of a cross-shaped semiconductor Hall sensor, saidcutouts having a geometry of one of a square, polygon, circle, ellipseand a combination of these forms, wherein said semiconductor Hall sensoris characterized in that: a film thickness, impurity concentration, thelength L1 and width W1 of the input side pattern and the length L2 andwidth W2 of the output side pattern are maintained; and at least one ofa resistance across input side terminals and a resistance across outputside terminals is 1.25 to 2.75times a resistance of a cross-shapedpattern consisting of a rectangle with the length L1 and width W1serving as the input side pattern, and a rectangle with the length L2and width W2 serving as the output side pattern.
 3. The semiconductorHall sensor as claimed in claim 1 or 2, wherein at least one of theresistance across the input side terminals and the resistance across theoutput side terminals is 1.5 to 2.5 times the resistance of thecross-shaped pattern consisting of the rectangle with the length L1 andwidth W1 serving as the input side pattern, and the rectangle with thelength L2 and width W2 serving as the output side pattern.
 4. Thesemiconductor Hall sensor as claimed in claim 3, wherein both theresistance across the input side terminals and the resistance across theoutput side terminals are 1.5 to 2.5 times the resistance of thecross-shaped pattern consisting of the rectangle with the length L1 andwidth W1 serving as the input side pattern, and the rectangle with thelength L2 and width W2 serving as the output side pattern.
 5. Thesemiconductor Hall sensor as claimed in any one of claims 2-4, whereinsaid consecutive two or four concave corners of said four concavecorners of the cross-shaped pattern have an acute angle at anintersection of the input terminal side pattern and the output terminalside pattern of the cross-shaped pattern.